testbench for VHDL serial port "http://scott2595.blogspot.com/2014/02/vhdl-code-for-serial-interface.html"

--testbench for http://scott2595.blogspot.com/2014/02/vhdl-code-for-serial-interface.html

library ieee;
use ieee.std_logic_1164.all;
use std.env.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
--library gate_work;
--use gate_work.top;

entity tb_spi is
end entity tb_spi;

architecture behavioral of tb_spi is
component top is
port (
    clk     : in std_logic;
    rst_n   : in std_logic;
    load    : in std_logic;
    slv_sel : in std_logic_vector(1 downto 0);
    din     : in std_logic_vector(4 downto 0);
    led0    : out std_logic_vector(4 downto 0);
    led1    : out std_logic_vector(4 downto 0);
    led2    : out std_logic_vector(4 downto 0)
);
end component;

signal clk     : std_logic;
signal rst_n   : std_logic;
signal load    : std_logic;
signal slv_sel : std_logic_vector(1 downto 0);
signal din     : std_logic_vector(4 downto 0);
signal led0    : std_logic_vector(4 downto 0);
signal led1    : std_logic_vector(4 downto 0);
signal led2    : std_logic_vector(4 downto 0);

begin
u_top: top port map (
    clk     => clk     ,
    rst_n   => rst_n   ,
    load    => load    ,
    slv_sel => slv_sel ,
    din     => din     ,
    led0    => led0    ,
    led1    => led1    ,
    led2    => led2    
);

process
begin
    clk <= '0';
    wait for 10 ns;
    clk <= '1';
    wait for 10 ns;
end process;

process
begin
    rst_n <= '1';
    wait for 100 ns;
    rst_n <= '0';
    wait for 100 ns;
    rst_n <= '1';
    wait;
end process;

process
variable seed1, seed2: positive;
variable int_rand: integer;
variable rand: real;                        
variable i: integer;
begin
    seed1 := 1;
    seed2 := 2;
    load <= '0';
    slv_sel <= "00";
    din <= "00000";
    wait for 300 ns;
    wait until rising_edge(clk);
    for i in 1 to 3 loop
        uniform(seed1, seed2, rand);
        int_rand := integer(trunc(rand * 31.0));
        din <= std_logic_vector(to_unsigned(int_rand, din'length));
        slv_sel <= std_logic_vector(to_unsigned(i, slv_sel'length));
        wait until rising_edge(clk);
        load <= '1';
        wait until rising_edge(clk);
        wait until rising_edge(clk);
        load <= '0';
        wait for 300 ns;
    end loop;
    finish(0);
end process;

end behavioral;