Friday, February 14, 2014

testbench for VHDL design "http://scott2595.blogspot.com/2014/02/clk-dividor-library-ieee-use-ieee.html"

--The VHDL design is in the links:
http://scott2595.blogspot.com/2014/02/clk-dividor-library-ieee-use-ieee.html
http://scott2595.blogspot.com/2014/02/use-vhdl-to-write-counter-with-more.html

library ieee;
use ieee.std_logic_1164.all;
use std.env.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
--library gate_work;
--use gate_work.top;

entity tb_counter is
generic (
    M : integer := 7;
    N : integer := 20
);
end entity tb_counter;

architecture behavioral of tb_counter is
component top
generic (
    M : integer := 7;
    N : integer := 12499999
);
port (
    clk           : in  std_logic;
    rst_n         : in  std_logic;
    selector      : in  std_logic_vector(1 downto 0);
    boundary_en   : in  std_logic;
    boundary_data : in  std_logic_vector(7 downto 0);
    data          : out std_logic_vector(7 downto 0);
    segment0      : out std_logic_vector(M-1 downto 0);
    segment1      : out std_logic_vector(M-1 downto 0);
    segment2      : out std_logic_vector(M-1 downto 0)
);
end component;

signal clk, rst_n    : std_logic;
signal selector      : std_logic_vector(1 downto 0);
signal boundary_en   : std_logic_vector(0 downto 0);
signal boundary_data : std_logic_vector(7 downto 0);
signal data          : std_logic_vector(7 downto 0);
signal segment0      : std_logic_vector(M-1 downto 0);
signal segment1      : std_logic_vector(M-1 downto 0);
signal segment2      : std_logic_vector(M-1 downto 0);

begin
 u_top: top generic map (
     M => M,
     N => N
) port map (
    clk           => clk,
    rst_n         => rst_n,
    selector      => selector,
    boundary_en   => boundary_en(0),
    boundary_data => boundary_data,
    data          => data,
    segment0      => segment0,
    segment1      => segment1,
    segment2      => segment2
);

process
begin
    clk <= '0';
    wait for 10 ns;
    clk <= '1';
    wait for 10 ns;
end process;

process
begin
    rst_n <= '1';
    wait for 100 ns;
    rst_n <= '0';
    wait for 100 ns;
    rst_n <= '1';
    wait;
end process;

process
variable seed1, seed2: positive := 1;
variable i: integer;
variable j: integer;
variable rand: real;                      
variable int_rand: integer;              
variable stim: std_logic_vector(11 downto 0);
begin
    for i in 0 to 1 loop
        for j in 0 to 3 loop
            uniform(seed1, seed2, rand);
            int_rand := integer(trunc(rand * 100.0 + 55.0));
            boundary_data <= std_logic_vector(to_unsigned(int_rand, boundary_data'length));
            boundary_en <=  std_logic_vector(to_unsigned(i, boundary_en'length));
            selector <=  std_logic_vector(to_unsigned(j, 2));
            wait for 300 us;
        end loop;
    end loop;
    finish(0);
end process;

end behavioral;

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