testbench for four bit adder design "http://scott2595.blogspot.com/2014/03/four-bit-adder.html"

--testbench for four bit adder design "http://scott2595.blogspot.com/2014/03/four-bit-adder.html"

library ieee;
use ieee.std_logic_1164.all;
use std.env.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
library work;
use work.top;

entity tb_adder is
end entity tb_adder;

architecture behavioral of tb_adder is
component top is
port (
    clk      : in  std_logic                    ;
    rst_n    : in  std_logic                    ;
    load     : in  std_logic                    ;
    a        : in  std_logic_vector(3 downto 0) ;
    b        : in  std_logic_vector(3 downto 0) ;
    segment0 : out std_logic_vector(6 downto 0) ;
    segment1 : out std_logic_vector(6 downto 0)
);
end component;

signal clk      : std_logic := '0';
signal rst_n    : std_logic;
signal load     : std_logic;
signal a        : std_logic_vector(3 downto 0);
signal b        : std_logic_vector(3 downto 0);
signal segment0 : std_logic_vector(6 downto 0);
signal segment1 : std_logic_vector(6 downto 0);

begin
u_top: top port map (
    clk      => clk      ,
    rst_n    => rst_n    ,
    load     => load     ,
    a        => a        ,
    b        => b        ,
    segment0 => segment0 ,
    segment1 => segment1
);

clk <= not clk after 10 ns;

process
begin
    rst_n <= '1';
    wait for 100 ns;
    rst_n <= '0';
    wait for 100 ns;
    rst_n <= '1';
    wait;
end process;

process
variable i, j: integer;
begin
    load <= '0';
    a <= x"0";
    b <= x"0";
    wait for 200 ns;
    for i in 0 to 15 loop
        for j in 0 to 15 loop
            a <= std_logic_vector(to_unsigned(i, a'length));
            b <= std_logic_vector(to_unsigned(j, b'length));
            wait for 20 ns;
            load <= '1';
            wait for 20 ns;
            load <= '0';
            wait for 100 ns;
        end loop;
    end loop;
    finish(0);
end process;

end behavioral;